In order to help reduce power in microprocessors while minimizing the impact to performance, prior art techniques for reducing processor clock frequency have been developed. Among these prior art techniques are architectures that divide the processor into various clock domains. For example, one prior art technique has a separate clock domain for the integer pipeline, a separate clock domain for the floating point pipeline, and a separate clock domain for memory access logic.
Using separate clock domains for each pipeline and/or memory access cluster can pose challenges to maintaining the performance of the processor due to the amount of overhead circuitry needed to control each clock domain.